PWM still has its place - it's not uncommon for high-end sigma deltas to have a multi-bit rather than one-bit output, which feeds into a PWM final output stage. It helps with numerical stability. I've used a similar technique to improve the audio output in FPGA projects where a simple 1st order SD feeds a 5-bit PWM. On the boards in question the output drivers seem to be somewhat asymmetric, making an SD quite noisy at higher clock frequencies. With the PWM final output stage the same effect manifests as a DC offset instead, since (when not saturated) the PWM has a fixed number of rising and falling edges in a given time period.